Synopsys has launched Custom Compiler, a design solution intended to close what the company calls a FinFET productivity gap. Dave Reed, director of marketing for Synopsys’ mixed signal and analogue ...

MOUNTAIN VIEW, Calif., Mar. 30, 2016 – Synopsys, Inc. (Nasdaq: SNPS) today unveiled Custom Compiler™, a new custom design solution that closes the FinFET productivity gap by shortening custom design ...

SAN JOSE, Calif. -- 26 Sep 2014 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that its digital and custom/analog tools have achieved ...

FinFETs are not simple to work with. They’re difficult to manufacture, tricky to design, and they run the risk of greatly increased dynamic power density—particularly at 14/16nm, where extra margin is ...

FinFET transistors are now in production at the major foundries, having gone from drawing board to products on the shelf in record time. FinFET adoption has been growing steadily because they deliver ...

In 5nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24nm. Fin depopulation is mandatory to enable area scaling ...

When making the transition from planar devices to FinFETs, IP design challenges arise that require education and experience when dealing with the complexities. Since the inception of the ...

The IC industry is already weeding out the candidates. In 2005, the Semiconductor Research Corp. (SRC), a chip R&D consortium, launched the Nanoelectronics Research Initiative (NRI), a group that is ...

(Nanowerk Spotlight) The emergence of the Internet of Everything demands additional improvements in today's – mostly rigid – electronics: They have to be flexible, stretchable, reconfigurable. Whereas ...

The Cadence custom/analog and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design ...